. @MarvellTech, @Microsoft & @Utimaco Drive Cloud Payment Security Modernization: Providing financial institutions with cloud-native, highly available security foundation through @Azure Payment HSM v2 shorturl.at/wKAq1 @MSCloud @MicrosoftARC @StevenDickens3 @stephensopko

Marvell has been named one of the Best Workplaces in Engineering for 2026, ranking 16th out of 100 companies recognized on the list, which is based on survey feedback from 14,000 U.S. employees analyzed by Great Place to Work. The recognition reflects what employees themselves report: opportunities to contribute and grow, meaningful work, pride in their teams and their company, and a culture that supports them. Combined with Marvell's recent Great Place to Work certification in seven countries, the two awards together paint a consistent picture of the environment the company has built. For engineers looking for a place to do consequential work alongside talented colleagues, the evidence is there. Read more about this recognition: mrvl.co/47vZ7Y2

Marvell has again been certified as a Great Place to Work, this time in a new high of seven countries: the United States, India, Vietnam, Singapore, Taiwan, Argentina, and Israel. The certification is based on employee survey data, and the results at Marvell are notable. Employees rated their experience highly across areas including being welcomed as new employees, being trusted with responsibility, and being treated as an equal, all significantly above what employees at a typical American company report. In the words of Executive Vice President and Chief Human Resources Officer Janice Hall: “A certification doesn’t create a great workplace—it recognizes one. The workplace we’re being recognized for is one we all help create every day through the way we work together, support one another and deliver for our customers. Congratulations to our teams across all seven certified countries.” Learn more about this honor: mrvl.co/4AEPXpP

October is Compliance Awareness Month at Marvell, and this year we’re doing something new. For the first time, Marvell has consolidated all mandatory annual compliance training into a single, focused month: Code of Conduct, Cybersecurity, Data Privacy, AI Ethics, Trade Compliance, and more. Not because it’s required, but because integrity is how we do the work. The month includes an executive video series featuring senior leaders sharing why integrity and compliance are inseparable from strong performance, a global site competition, and a featured guest speaker event on October 29 with Tom Hardin, the former Wall Street analyst turned FBI informant whose story offers a compelling firsthand perspective on ethical decision-making under pressure. At Marvell, compliance is not a checkbox. It is part of who we are.

Please join Chairman and CEO Matt Murphy and members of Marvell’s executive leadership team, to hear about the company’s strategy, growth opportunities, and role in enabling the next generation of AI and data center infrastructure. The event livestream will be held here: mrvl.co/3TzCLBM

Marvell Director of Packaging Suresh Pothukuchi will deliver a keynote at the 59th International Symposium on Microelectronics in Boston, Massachusetts, addressing how photonics packaging is breaking interconnect barriers for the next era of compute, memory, and AI systems. Suresh brings more than two decades of experience in silicon, package, and system co-design, including extensive work on EMIB, Foveros, optical I/O, and hybrid bonding across 2.5D, 3D, and 3.5D integration. He joined Marvell following the acquisition of Celestial AI, where he led systems packaging architecture for Photonic Fabric technology. The IMAPS Symposium is one of the most respected forums for advanced packaging and microelectronics technical content, with this year's theme reflecting how central intelligent packaging has become to AI infrastructure. Learn more: mrvl.co/4AzaFax

KV cache is growing exponentially with agentic AI, and the memory hierarchy was not designed to handle it. HBM fills up. DRAM fills up. Once workloads spill over to storage, latency climbs and cluster performance drops. In this NextGenInfra clip from AI Infra Summit 2026, Marvell Senior Director of Product Management, Photonic Fabric Business Unit, Ravi Mahatme, explains why a new memory tier is needed and how optical interconnects make it possible, delivering the bandwidth and reach required to turn multiple racks into a single shared memory space. Watch the full conversation with Ravi and Preet Virk, Senior Vice President and General Manager of the Photonic Fabric Business Unit: mrvl.co/4dHvVkq

AI silicon was once judged by a simple scorecard: win one of a handful of major custom XPU design slots, or you’ve lost. @MarvellTech CEO Matt Murphy tells @danielnewmanUV and @PatrickMoorhead that the opportunity is much broader, with dozens of custom silicon and XPU attach wins across the AI infrastructure stack. “This market is not a zero-sum game.” $MRVL

At @ECOC_Exhibition 2026, Marvell demonstrated next-generation 2nm DSP chips powering 1.6T ZR coherent C- and L-Band connectivity and 1.6T coherent-lite O-band connectivity, two technologies optimized to deliver high-bandwidth connectivity within and between data center facilities and laying the groundwork for 3.2T. The chip-level demonstration highlighted the performance achievable at the 2nm node, extending Marvell's coherent product offerings to 1.6T across both long-reach ZR and shorter-reach coherent-lite O-band applications that are increasingly relevant as data center campuses grow in scale and complexity.

Marvell has won the 2026 EDGE Award from @ElectronicDesgn in the Machine Vision and Optical Components and Systems category for the COLORZ 1600, the industry's first 1.6T ZR/ZR+ data center interconnect pluggable, powered by the Marvell Electra 2nm coherent DSP. COLORZ 1600 connects campus, metro, and regional data centers at 1.6T across distances up to 1,000km, purpose-built for the multi-site AI infrastructure architectures that hyperscalers are deploying today. Marvell was also recognized as an honoree in the Electronic Components category for the Structera S 60260, the industry's first 260-lane PCIe 6.0 switch, which flattens scale-up network topology to deliver higher density and lower latency. Read the full article: mrvl.co/4z08mvj #EDGE26

Flooding affects 76% of semiconductor manufacturing sites worldwide. Water scarcity, often assumed to be the primary concern, affects only 16%. The gap between perception and reality is one of the more striking findings in recent research led by Marvell Senior Sustainability Program Manager Alua Suleimenova in partnership with SEMI. Published in Voice, the journal of the Singapore Semiconductor Industry Association, Alua's article draws on two industry reports examining how climate and water risks are emerging as material business risks for the semiconductor supply chain. A single fabrication facility can consume up to 10 million gallons of water per day, and more than 40% of semiconductor facilities announced since 2021 are located in watersheds projected to face high or extremely high water stress by 2030 to 2040. The article makes the case that resilience, not just compliance, is the strategic imperative. Read the full article: mrvl.co/4z1kXOU

Every FLOP left idle and every bit of memory left stranded is CapEx that isn't generating return. In this clip from AI Infra Summit 2026, Marvell Senior Vice President of the Photonic Fabric Business Unit Preet Virk makes the case for why connectivity has become the key to unlocking AI data center efficiency. Watch the full conversation with Preet and Senior Director of Product Management Ravi Mahatme at NextGenInfra: mrvl.co/4AsnV0p

Structera X CXL memory expansion is now jointly validated with the NVIDIA Vera CPU platform, confirming consistent CXL 2.0 compliance and full feature support across device enumeration, resets, data exchange, and firmware update. With validated interoperability now spanning several partners, Structera X is the most broadly validated CXL memory expansion solution in the industry. For cloud operators and OEMs managing heterogeneous server fleets, that breadth means deploying CXL memory expansion without re-qualifying for each new platform. Marvell's Arifur Rahman details what was tested, what was confirmed, and what it means for customers building CXL-enabled AI infrastructure at scale: mrvl.co/4yeFpfm

Converge Network Digest covers Marvell's ECOC 2026 demonstrations in depth, with particular attention to what the move to 400G per lane means for the path to 3.2T optical connectivity. The article walks through all five demonstration categories, from 2nm PAM4 and coherent technologies to the 102.4 Tbps CPO platform, and frames why Marvell is applying 2nm across PAM4, ZR/ZR+, and coherent-lite simultaneously rather than treating it as a single-product node transition. It also notes the breadth of AI connectivity domains covered: scale-out, scale-up, scale-across, and shorter-reach campus interconnects. Read the full article: mrvl.co/4iKHTNG

Marvell delivered a dynamic presence at AI Infra Summit 2026, showcasing its comprehensive portfolio of AI data center connectivity and memory solutions across four speaking sessions and a full booth of live demonstrations. The Marvell Teralynx T100, the industry's first 102 Tbps Ethernet switch purpose-built for AI, was a centerpiece of the booth, making its first live public appearance since its announcement at Computex in June. Alongside it, demonstrations spanned Photonic Fabric technology for multi-rack optical memory sharing, the RELIANT interconnect telemetry platform, PCIe-based scale-up switching, CXL memory expansion and near-memory acceleration, and high-speed storage solutions. Among four Marvell presentations, Executive Vice President and General Manager of the Data Center Networking Business Group Dave Lazovsky delivered a keynote on AI inference at scale, underscoring the message that ran throughout the show: connectivity now sits at the center of AI infrastructure performance, shaping bandwidth, latency, power consumption, and the economics of deploying AI at scale. #AIInfraSummit

Marvell is demonstrating its co-packaged optics platform at @ECOC_Exhibition, including a 102.4 Tbps capable CPO implementation built on class-leading silicon photonics. The physics driving CPO adoption are straightforward. As per-lane speeds in scale-up fabrics increase, the distance over which signals can travel over passive copper falls. AI pods spanning multiple racks require longer interconnect distances than copper can support. CPO brings optical elements directly into the package alongside the IC, reducing distance, improving performance, and lowering power consumption. The demonstration at booth 2002 showcases 200G per lane with aggregate bandwidth in multiples of 6.4 Tbps, alongside detachable ELSFPs for rapid laser replacement and simplified manufacturability. #ECOC26 #ECOCExhibition

Memory capacity has become one of the defining constraints on AI infrastructure performance. Marvell is demonstrating a solution at @ECOC_Exhibition that approaches the problem from a different direction, and new category. The Photonic Fabric™ technology demonstration at Booth 2002 shows optical interconnects which can create shared memory pools across multiple racks, enabling compute and memory to scale independently. #ECOC26 #ECOCExhibition

When memory leaves the server and rides a switched fabric, is it still memory, or has it become a network? That question drove MemNetAI, the first workshop on Memory-Semantic Networking for AI-Scale Systems, launched by Marvell with researchers from IIT Hyderabad and IIIT Delhi at ACM SIGCOMM 2026 in Denver. The workshop brought together speakers from Cornell and industry experts to address a convergence that AI infrastructure is forcing: keeping accelerators fed with data is as much a networking problem as one of memory. Talks covered CXL memory expansion, GPU memory tracing, photonic scale-up interconnects, and memory disaggregation, with a closing panel debating whether the boundary between memory and network still means anything at the bandwidth and latency levels AI systems demand. Director of Custom Cloud Solutions Abed Mohammad Kamaluddin recaps the day's key themes and why they matter for the future of AI infrastructure: mrvl.co/3TK5ns0

Stop by Booth 2002 at @ECOC_Exhibition to witness one of the core building blocks of next-generation AI networking. Marvell's multi-protocol 224G LR SerDes IP block built on 2nm silicon platform, with high-speed data transmission over a 2.5-meter copper connection, enables 200G-per-lane connectivity, a critical step towards 1.6Tbps Ethernet, which helps AI and cloud infrastructure to move significantly more data with greater efficiency, paving the way for next-gen networking and the data center architectures that come with it. #ECOC26 #ECOCExhibition