🚨 Kirin 9050 Pro is an Engineering MARVEL!
You've never seen a Chip like this with Double Die fit on top of Each other.
Let me deep dive about this new Double Die & Logic Folding Design.
So, Kirin 9050 Pro features double Die Layout. Each takes an Area of 120.6mm² & Combined at 241.3mm². For Reference Kirin 9030 Pro has a Chip Area of 141.7mm². It's about a 70% more Area if the Double Die is Considered.
But how is the Double Die Structurally Possible??
Huawei & Hisilicon made this Possible. The Dies are connected through Vertical Copper to Copper Hybrid Bonding.
Huawei says the First-generation implementation uses approximately 1.5 µm hybrid-bonding Pitch and around 50 Million vertical Connections between the Layers.
It uses TSVs (through Silicon Vias) to connect the two Dies for Electricity/signal flow & a Vertical Connection.
For Kirin 9050 Pro, Hisilicon uses 80,000 of these TSVs to connect the Chip to the Substrate & these TSVs takes about 8% of usable Area.
The Primary die (the first Half) contents Execution Units such as Integers, Floating Point Units & Load/store Units & the Secondary contents necessary Caches for the CPU. These are linked directly by Extremely dense Metal Layers & Copper-to-Copper Hybrid Bonds.
🔶 Main Die — This contains the more computationally intensive portions:
CPU
GPU
NPU
DSP
ISP
Memory Controller
Modem
SLC Controller
L/S (Load/Store)
INT (integer/interrupt-related logic)
FPU
🔶 Secondary Die — The left die is primarily devoted to cache and I/O, including:
L1 / L2 / L3 cache
SLC — 12 MB
ISP
DSP
NPU
LPDDR PHY
USB 3.2
RF-I/F
Various PLL / I/O blocks
This 3D Folding Design helps shortening the Distance for Electric Flow that reduces the Latency & Ultimately yields Lower Power Consumption & Lower Voltage at the Same relative Frequency.
Bottom line, The Kirin 9050 Pro's
Logic-folding / Two-die design separates the low-power, Area-Heavy cache & I/O logic from the High-power Compute logic, allowing Huawei to pack more functionality into the Package while concentrating the thermally demanding CPU/GPU/NPU blocks on the Main die.