What if RISC-V had 1024 registers instead of 32? Can that solve register spilling & improve zkVMs? Claude and I implemented this experiment in LLVM's RV32 backend and integrated it with OpenVM for e2e proofs. Full results and write-up link below \/

Apr 17, 2026 · 9:53 AM UTC

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Full write-up: leonardoalt.github.io/riscv-…

Giving RISC-V 1024 registers for zkVMs

General purpose zkVMs like OpenVM, SP1, ZisK pick RISC-V as their main source ISA because of its simplicity. It is a modern, minimal, well-understood ISA with mature toolchains. But RISC-V...

leoalt.de
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Replying to @leonardoalt
Whoa. Cool. Where can I follow the work and/or read the code?
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The full write-up has all relevant links
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Replying to @leonardoalt
Risc 5 10?
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Replying to @leonardoalt
This is awesome, nice work!
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Replying to @leonardoalt
Really cool writeup, and the idea of having infinite registers is truly intriguing. Kudos!
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Replying to @leonardoalt
In 2023, I distributed llama2 matmul to 4c8t CPU each 16 xmm regs used as 8t x 16 x 4 x r32 = 512 x 32 bit regs to get benefit of registers & L1 caches. 1024 x 32 bit regs would remove the need to slice data to L1 caches & make all threads finish in 50-80ns window on i7-2630QM.
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